1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a redundancy circuit, and a method thereof which can increase the redundancy efficiency during performing of a column redundancy operation.
2. Description of the Related Art
A conventional semiconductor memory device replaces a column select signal line connected to a defective partial block of a memory with a redundant column select signal line connected to a redundant partial block of each of memory cell array blocks, when partial blocks of a plurality of memory cell array blocks are defective. Here, a partial block is a block including memory cells connected to one column select signal line. However, in this case a partial block of not only a defective block, but also partial blocks of other memory cell array blocks connected to the same column select signal line as the defective partial block, are replaced with a redundant partial block.
For example, in a case that the number of redundant partial blocks of each of memory cell array blocks is one and there is a defect in one partial block of one memory cell array block among a plurality of memory cell array blocks, the conventional semiconductor memory device replaces a column select signal line connected to a defective partial block with a redundant column select signal line connected to a redundant partial block. Then, partial blocks of other memory cell array blocks connected to the defective column select signal line are also replaced with a redundant partial block.
However, if there are defects in other partial blocks of other memory cell array blocks, this semiconductor memory device cannot be repaired. That is, there is a problem that the conventional semiconductor memory device can not be repaired when the number of defective column select signal lines that occur in all the memory cell array blocks exceeds the number of redundant column select signal lines. This is because a redundancy circuit of the conventional semiconductor memory device is configured so that a column select signal line connected to partial blocks located in the identical position among a plurality of memory cell array blocks is replaced with a redundant column select signal line. This problem may occur in a semiconductor memory device of a stack bank structure. Therefore, a conventional semiconductor memory device has a problem that redundancy efficiency is poor with respect to performing column redundancy.
A redundancy circuit of a conventional semiconductor memory device directed to solving the above problem is disclosed in U.S. Pat. No. 5,325,334, entitled "Column Redundancy Circuit of a Semiconductor Memory Device". This circuit is configured to select a defective block by a block selection control circuit during performing of a column redundancy operation, and to generate a redundant enable signal by programming a column address of a defective block.
The above noted redundancy circuit of the conventional semiconductor memory device can increase the redundancy efficiency by performing a redundancy operation selectively by use of a block select signal, so as to select defective memory cell array blocks. However, the above noted redundancy circuit of the conventional semiconductor memory device has a problem in that the redundancy efficiency increases for regular defects, but decreases for irregular defects.
A redundancy method of a conventional semiconductor memory device will now be described as follows with reference to the accompanying drawings. FIG. 1 is a configuration of a memory cell array of a conventional semiconductor memory device, including eight memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH, and a word line WL is arranged in a horizontal direction in each of the eight memory cell array blocks. A local data input/output line LIO is arranged between neighboring memory cell array blocks, and column select signal lines CSL1, CSL2, . . . and CSLn and a redundant column select signal line RCSL are arranged in a vertical direction.
In FIG. 1, partial blocks indicated by a dotted line are partial blocks of each of the memory cell array blocks and are connected to column select signal lines CSL1, CSL2, . . . and CSLn. Partial blocks indicated by a solid line are redundant partial blocks and are connected to the redundant column select signal line RCSL. Each of memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH respectively comprises n memory cell partial blocks and redundant partial blocks BLA1, . . . , BLAn, RBLA; BLB1, . . . , BLBn, RBLB; . . . and BLH1, . . . , BLHn, RBLH. A redundancy method of the prior semiconductor memory device will be described as follows using FIG. 1.
If a memory cell of a partial block BLA2 of a memory cell array block BLA connected to a column select signal line CSL2 is defective, a column select signal line CSL2 is replaced with a redundant column select signal line RCSL when a corresponding column address is inputted, without regard to whichever block is selected among memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH. However, in a case that a partial block BLA1 of a memory cell array block BLA and a partial block BLB2 of a memory cell array block BLB are defective at the same time, only one line of a column select signal line CSL1 or a column select signal line CSL2 can be replaced with a redundant column select signal line RCSL. That is, partial blocks BLA1, BLB1, . . . and BLH1 connected to a column select signal line CSL1 are replaced with redundant partial blocks RBLA, RBLB, . . . and RBLH respectively, or partial blocks BLA2, BLB2, . . . and BLH2 connected to a column select signal line CSL2 are replaced with redundant partial blocks RBLA, RBLB, . . . and RBLH respectively.
Therefore, in a case that there is only one redundant column select signal line RCSL as shown in FIG. 1, one column select signal line of all the memory cell array blocks is replaced with a redundant column select signal line, and other column select signal lines can not be replaced with a redundant column select signal line.
FIG. 2 is a configuration of an embodiment of a memory cell array block BLA and a peripheral circuit thereof shown in FIG. 1, wherein a partial block BLA1 comprises memory cells MC connected between four bit line pairs BL1, BL1B; BL2, BL2B; BL3, BL3B and BL4, BL4B and word lines WL1, . . . and WLn. The peripheral circuit of the partial block BLA1 comprises sense amplifiers 20-1, 20-2, 20-3 and 20-4 for amplifying input/output data that are connected to four bit line pairs BL1, BL1B; BL2, BL2B; BL3, BL3B and BL4, BL4B respectively, and comprises data input/output gates 22-1, 22-2, 22-3 and 22-4 which are connected between sense amplifiers 20-1, 20-2, 20-3 and 20-4 and local data input/output line pairs LIO1, LIO1B; LIO2, LIO2B; LIO3, LIO3B and LIO4, LIO4B and which are for transmitting data in response to a signal applied to a column select signal line CSL1. The configuration of the other partial blocks and peripheral circuits are the same as the configuration of partial block BLA1 and the corresponding peripheral circuit.
A data input/output operation in FIG. 2 will be described as follows. If a memory cell array BLA is selected and a signal applied to a column select signal line CSL1 is activated, data input/output gates 22-1, 22-2, 22-3 and 22-4 of partial block BLA1 are turned on and data is transmitted between bit line pairs BL1, BL1 B; BL2, BL2B; BL3, BL3B and BL4, BL4B of the partial block BLA1 and local data input/output line pairs LIO1, LIO1B; LIO2, LIO2B; LIO3, LIO3B and LIO4, LIO4B.
A redundancy method of the conventional semiconductor memory device will be described as follows using FIG. 1 and FIG. 2. In a case that a memory cell in a partial block BLA1 of a memory cell array block BLA is defective, a column select signal line CSL1 is replaced with a redundant column select signal line RCSL. Accordingly, a redundancy circuit of the conventional semiconductor memory device replaces the column select signal line CSL1 with the redundant column select signal line RCSL, even if memory cell array blocks other than the memory cell array block BLA are not selected.
That is, as known from the configuration of FIG. 2, there is a problem in that the conventional semiconductor memory device can not be repaired in a case wherein the number of column select signal lines which are to be replaced because of a defect in different partial blocks of different memory cell array blocks, exceeds the number of redundant column select signal lines of a redundant partial block.
FIG. 3 is a configuration of a semiconductor memory device of the conventional stack bank structure, including eight memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH. Each of the memory cell array blocks respectively comprises four partial blocks BLAA, BLAB, BLAC, BLAD; BLBA, BLBB, BLBC, BLBD; . . . and BLHA, BLHB, BLHC, BLHD. Each of two left and right neighboring partial blocks comprise k partial blocks and a redundant partial block. That is, partial blocks BLAA and BLAB on the left comprise k partial blocks BLA1, . . . and BLAk and a redundant partial block LRBLA, and partial blocks BLAC and BLAD on the right comprise a redundant partial block RRBLA and k partial blocks BLA1, . . . and BLAk.
Also in FIG. 3, word lines WL and local data input/output lines LIO are arranged horizontally and global data input/output line groups GIOG1 and GIOG2 are arranged vertically. A local data input/output line LIO is constituted as being separated within a unit of two neighboring partial blocks of each of the blocks, and each of global data input/output line groups GIOG1 and GIOG2 are arranged between two neighboring partial blocks on the left and right. Column select signals CSL1, . . . and CSLk transfer data between a corresponding partial block of two neighboring partial blocks on the left and right and corresponding global data input/output line groups GIOG1 and GIOG2.
In the configuration of FIG. 3, in a redundancy method in a case wherein memory cells of two partial blocks on the left are defective, one column select signal line connected to the defective memory cell is replaced with a redundant column select signal LRCSL of the left redundant partial blocks LRBLA, LRBLB, LRBLC, LRBLD, LRBLE, LRBLF, LRBLG and LRBLH. However, the other defective column select signal line can not be repaired. That is, a semiconductor memory device shown in FIG. 3 can be repaired only when one column select signal line is defective, since there is one redundant column select signal line on the left. The semiconductor memory device can not be repaired in a case wherein more than two column select signal lines are defective.
Similarly, in a redundancy method in a case wherein memory cells of two partial blocks on the right are defective, one column select signal line connected to the defective memory cell is replaced with a redundant column select signal RRCSL of the right redundant partial blocks RRBLA, RRBLB, RRBLC, RRBLD, RRBLE, RRBLF, RRBLG and RRBLH. Also in this case similarly to the redundancy operation on the left, the semiconductor memory device can be repaired only when one column select signal line is defective, since there is one redundant column select signal line on the right. That is, the semiconductor memory device can not be repaired in a case that the number of defective column select signal lines that occur in different partial blocks of different memory cell array blocks exceeds the number of redundant column select signal lines of a redundant partial block.
FIG. 4 is a circuit diagram showing the configuration of an embodiment of a memory cell array block BLA and a peripheral circuit thereof for the block diagram shown in FIG. 3. The configuration of a partial block BLA1 of a partial block BLAA of a memory cell array block BLA is the same as the configuration of the partial block BLA1 shown in FIG. 2. A peripheral circuit of a partial block BLA1 comprises sense amplifiers 30-1, 30-2, 30-3 and 30-4 connected between bit line pairs BL1, BL1B; BL2, BL2B; BL3, BL3B and BL4, BL4B, and comprises data input/output gates 32-1, 32-2, 32-3 and 32-4 for controlling data transmission between local data input/output line pairs LIO1, LIO1B; LIO2, LIO2B; LIO3, LIO3B and LIO4, LIO4B and sense amplifiers 30-1, 30-2, 30-3 and 30-4. The configuration of the other partial blocks and peripheral circuits are the same as the configuration of the partial block BLA1. The symbols and numbers of the peripheral circuit are marked identically in the drawing.
In a case that the partial block BLA1 of a memory cell array block BLA in FIG. 4 is defective, a redundancy method of the conventional semiconductor memory device replaces a column select signal line CSL1 with a redundant column select signal line LRCSL, when a column address for selecting the column select signal line CSL1 is applied. However, a redundancy circuit of the conventional semiconductor memory device replaces the column select signal line CSL1 with the redundant column select signal line LRCSL, and also replaces other memory cell array blocks BLB, BLC, BLD, BLE, BLF, BLG and BLH other than the memory cell array block BLA selected.
Therefore, there is a problem that the semiconductor memory device shown in FIG. 3 replaces only one column select signal line of column select signal lines CSL1 and CSLk connected to partial blocks BLA1 and BLBk with a redundant column select signal line LRCSL, but can not replace another column select signal line with the redundant column select signal line LRCSL if a partial block BLA1 of a memory cell array block BLA and a partial block BLBk of a memory cell array block BLB are defective. Accordingly, the redundancy method of the conventional semiconductor memory device has a problem in that redundancy efficiency is poor.